650V功率VDMOS結終端擴展優(yōu)化設計
發(fā)布時間：2018-12-25 11:07
【摘要】：高壓VDMOS器件需要借助終端結構來緩解結彎曲引起的曲率效應。在VDMOS器件設計中,高擊穿電壓、短終端長度、低漏電流和低表面電場峰值等性能參數的終端結構對芯片的穩(wěn)定性和可靠性至關重要。聯合傳統(tǒng)的場板、場限環(huán)、結終端擴展(JTE)等終端技術形成的復合終端結構在學術界獲得廣泛研究。本文對650V VDMOS器件的多場限環(huán)(MFLR)、復合場板多場限環(huán)(FP-MFLR)、單區(qū)JTE和復合場板JTE(FP-JTE)四種終端結構進行優(yōu)化設計。通過分析PN結耐壓機理,采用碰撞電離率Lackner模型對650V VDMOS元胞結構進行仿真設計。并對其靜態(tài)參數進行測試,擊穿電壓達到773.3V,導通電阻為6.73Ω,閾值電壓為2.66V,滿足了設計要求。此結構為穿通型設計,最大電場為2.55×10~5V/cm。在確定元胞結構外延參數的基礎上,不改變工藝條件對單場限環(huán)、多場限環(huán)、金屬與多晶硅復合場板及單區(qū)JTE結構進行優(yōu)化。研究發(fā)現,主結與場限環(huán)同時擊穿時,擊穿點并不在同一水平線上,而是由內向外逐漸靠近硅表面;最外環(huán)為非穿通型擊穿,其余各環(huán)為穿通型擊穿,各環(huán)結表面電場峰值從主結處由內向外逐漸增大,主結處表面電場峰值略低于場限環(huán)處;金屬場板完全籠蓋住多晶硅,適當的多晶硅和金屬場板長度使表面電場呈現三個峰值,多晶硅場板拉低主結與金屬場板兩處的表面電場峰值;密封保護環(huán)或者溝道截止環(huán)放置在耗盡層邊界外以避免對終端結構的耐壓造成影響�；诖�,設計的6FLRs終端結構耐壓達到679V,在183.8μm的終端長度下,將表面電場峰值降低至2.34×10~5V/cm;將FP-MFLR結構的終端長度縮小至171.8μm,其耐壓達到700.0V,表面電場低至2.11×10~5V/cm;單區(qū)JTE結構的耐壓為713.4V,終端長度進一步縮小至141.8μm,表面電場峰值在四種結構中最小,值為1.9×10~5V/cm;FP-JTE結構的擊穿電壓達到最大,值為757.7V,耐壓效率98%,幾乎接近元胞區(qū)結構的擊穿電壓,具有最小的終端長度139.2μm,表面電場峰值為2.28×1 05V/cm。除此之外,四種終端結構均相容于傳統(tǒng)工藝,操作方便易實現。同時,FP-MFLR與FP-JTE結構受界面電荷影響小,穩(wěn)定性和可靠性相對較高。
[Abstract]:High voltage VDMOS devices need terminal structure to mitigate curvature effect caused by junction bending. In the design of VDMOS devices, the terminal structure with high breakdown voltage, short terminal length, low leakage current and low surface electric field peak value is very important to the stability and reliability of the chip. The structure of composite terminal formed by combining traditional terminal technologies such as field plate, field limiting ring and junction terminal extension (JTE) has been widely studied in academia. In this paper, four kinds of terminal structures of multifield limiting loop (FP-MFLR), single zone JTE and composite field plate JTE (FP-JTE) for 650V VDMOS devices are optimized. By analyzing the voltage resistance mechanism of PN junction and using the Lackner model of collision ionization rate, the cell structure of 650 V VDMOS was simulated and designed. The static parameters are tested, the breakdown voltage is 773.3 V, the on-resistance is 6.73 惟, and the threshold voltage is 2.66 V, which meets the design requirements. The maximum electric field is 2.55 脳 10 ~ (5) V / cm ~ (-1). On the basis of determining the cell structure epitaxial parameters, single field limiting ring, multiple field limiting ring, metal and polysilicon composite field plate and single zone JTE structure are optimized without changing the process conditions. It is found that when the main junction and the field limiting ring break down simultaneously, the breakdown point is not on the same horizontal line, but is gradually approaching the silicon surface from the inside out. The outmost ring is non-perforated breakdown, the other rings are perforated breakdown, the peak value of surface electric field increases from the main junction to the outside, and the peak value of the surface electric field at the main junction is slightly lower than that at the field limiting ring. The metal field plate completely covers the polycrystalline silicon, the proper length of the polycrystalline silicon and metal field plate makes the surface electric field show three peaks, and the polysilicon field plate lowers the surface electric field peak at the main junction and the metal field plate. The seal protection ring or the channel cutoff ring is placed outside the depletion layer boundary to avoid the pressure resistance of the terminal structure. Based on this, the designed 6FLRs terminal structure can withstand voltage up to 679V, and the peak value of surface electric field is reduced to 2.34 脳 10 ~ (5) V / cm at a terminal length of 183.8 渭 m. The terminal length of FP-MFLR structure is reduced to 171.8 渭 m, the voltage resistance is 700.0V, and the surface electric field is as low as 2.11 脳 10 ~ (5) V / cm. The voltage resistance of single-zone JTE structure is 713.4V, the terminal length is further reduced to 141.8 渭 m, and the peak value of surface electric field is the smallest among the four structures, with a value of 1.9 脳 10 ~ (5) V / cm. The breakdown voltage of FP-JTE structure reaches the maximum value (757.7V). The breakdown voltage of the FP-JTE structure is almost close to that of the cellular structure. It has the smallest terminal length of 139.2 渭 m and the peak surface electric field of 2.28 脳 10 5 V / cm ~ (-1). In addition, the four terminal structures are compatible with the traditional technology, easy to operate. At the same time, the structure of FP-MFLR and FP-JTE is less affected by interfacial charge, and its stability and reliability are relatively high.
【學位授予單位】：西南交通大學
【學位級別】：碩士
【學位授予年份】：2017
【分類號】：TN386
本文編號：2391074
[Abstract]:High voltage VDMOS devices need terminal structure to mitigate curvature effect caused by junction bending. In the design of VDMOS devices, the terminal structure with high breakdown voltage, short terminal length, low leakage current and low surface electric field peak value is very important to the stability and reliability of the chip. The structure of composite terminal formed by combining traditional terminal technologies such as field plate, field limiting ring and junction terminal extension (JTE) has been widely studied in academia. In this paper, four kinds of terminal structures of multifield limiting loop (FP-MFLR), single zone JTE and composite field plate JTE (FP-JTE) for 650V VDMOS devices are optimized. By analyzing the voltage resistance mechanism of PN junction and using the Lackner model of collision ionization rate, the cell structure of 650 V VDMOS was simulated and designed. The static parameters are tested, the breakdown voltage is 773.3 V, the on-resistance is 6.73 惟, and the threshold voltage is 2.66 V, which meets the design requirements. The maximum electric field is 2.55 脳 10 ~ (5) V / cm ~ (-1). On the basis of determining the cell structure epitaxial parameters, single field limiting ring, multiple field limiting ring, metal and polysilicon composite field plate and single zone JTE structure are optimized without changing the process conditions. It is found that when the main junction and the field limiting ring break down simultaneously, the breakdown point is not on the same horizontal line, but is gradually approaching the silicon surface from the inside out. The outmost ring is non-perforated breakdown, the other rings are perforated breakdown, the peak value of surface electric field increases from the main junction to the outside, and the peak value of the surface electric field at the main junction is slightly lower than that at the field limiting ring. The metal field plate completely covers the polycrystalline silicon, the proper length of the polycrystalline silicon and metal field plate makes the surface electric field show three peaks, and the polysilicon field plate lowers the surface electric field peak at the main junction and the metal field plate. The seal protection ring or the channel cutoff ring is placed outside the depletion layer boundary to avoid the pressure resistance of the terminal structure. Based on this, the designed 6FLRs terminal structure can withstand voltage up to 679V, and the peak value of surface electric field is reduced to 2.34 脳 10 ~ (5) V / cm at a terminal length of 183.8 渭 m. The terminal length of FP-MFLR structure is reduced to 171.8 渭 m, the voltage resistance is 700.0V, and the surface electric field is as low as 2.11 脳 10 ~ (5) V / cm. The voltage resistance of single-zone JTE structure is 713.4V, the terminal length is further reduced to 141.8 渭 m, and the peak value of surface electric field is the smallest among the four structures, with a value of 1.9 脳 10 ~ (5) V / cm. The breakdown voltage of FP-JTE structure reaches the maximum value (757.7V). The breakdown voltage of the FP-JTE structure is almost close to that of the cellular structure. It has the smallest terminal length of 139.2 渭 m and the peak surface electric field of 2.28 脳 10 5 V / cm ~ (-1). In addition, the four terminal structures are compatible with the traditional technology, easy to operate. At the same time, the structure of FP-MFLR and FP-JTE is less affected by interfacial charge, and its stability and reliability are relatively high.
【學位授予單位】：西南交通大學
【學位級別】：碩士
【學位授予年份】：2017
【分類號】：TN386
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