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大規(guī)模陣列SPAD淬滅電路設(shè)計(jì)

發(fā)布時(shí)間:2018-12-27 08:33
【摘要】:單光子雪崩光電二極管(Single Photo Avalanche Diode, SPAD)探測器的快速傳感和淬滅是實(shí)現(xiàn)單光子探測的關(guān)鍵前提條件。隨著SPAD研究的不斷發(fā)展,器件陣列規(guī)模不斷擴(kuò)大,使得與之匹配的淬滅電路設(shè)計(jì)難度加大。而淬滅電路性能的優(yōu)劣直接影響著探測系統(tǒng)的整體性能。本文針對應(yīng)用于大規(guī)模陣列SPAD探測器的淬滅電路進(jìn)行了深入地研究。本文在面積和功耗嚴(yán)格約束的條件下,提出了兩種應(yīng)用于大規(guī)模陣列SPAD的淬滅電路設(shè)計(jì):電阻感應(yīng)淬滅電路和電容感應(yīng)淬滅電路。兩種電路采用相同的結(jié)構(gòu)框架,結(jié)合主動、門控兩種淬滅方式,通過電阻或電容感應(yīng)雪崩電流。電阻感應(yīng)淬滅電路采用基于失調(diào)控制的差分放大低閾值檢測電路,打破傳統(tǒng)設(shè)計(jì)中淬滅電路的檢測閾值必須大于MOS管開啟電壓的約束,實(shí)現(xiàn)對雪崩電流的快速檢測。電容感應(yīng)淬滅電路采用SPAD寄生電容感應(yīng)雪崩電流,極大程度地縮減了版圖面積;同時(shí)采用反相器作為檢測電路,加快了淬滅過程,降低了系統(tǒng)功耗。兩種淬滅電路都采用TSMC 0.35μm CMOS工藝完成仿真設(shè)計(jì)和流片驗(yàn)證。兩者后仿真結(jié)果均滿足設(shè)計(jì)指標(biāo)要求,可以檢測低至200μA的雪崩電流,在2ns內(nèi)實(shí)現(xiàn)復(fù)位,并在5ns內(nèi)輸出單光子響應(yīng)脈沖供后級讀出電路處理。該結(jié)果表明,與國內(nèi)外現(xiàn)有研究成果相比,本文設(shè)計(jì)的淬滅電路在復(fù)位和淬滅時(shí)間方面具有一定的優(yōu)勢。兩種電路分別通過8×8和64×64陣列規(guī)模的讀出電路系統(tǒng)進(jìn)行流片驗(yàn)證。芯片測試結(jié)果表明,兩種淬滅電路都可以實(shí)現(xiàn)感應(yīng)并淬滅雪崩電流等功能。但是由于大陣列系統(tǒng)版圖寄生效應(yīng)等的影響,測試結(jié)果與仿真結(jié)果存在一定的差距,論文對此給出了詳細(xì)的分析和改進(jìn)方法。
[Abstract]:Fast sensing and quenching of single photon avalanche photodiode (Single Photo Avalanche Diode, SPAD) detector is a key prerequisite for single photon detection. With the development of SPAD research, the scale of device array is expanding, which makes it more difficult to design the matched quenched circuit. The performance of quenching circuit directly affects the overall performance of the detection system. In this paper, the quenching circuit used in large scale array SPAD detectors is studied. In this paper, under the condition of strict area and power constraints, two kinds of quenching circuit design for large-scale array SPAD are proposed: resistive induction quenching circuit and capacitive induction quenching circuit. The two circuits adopt the same structure frame, combined with active and gated quenching methods, and induce avalanche current by resistance or capacitance. Resistance induction quenching circuit adopts differential amplification low threshold detection circuit based on offset control. The detection threshold of quenching circuit in traditional design must be greater than the limit of MOS switch on voltage to realize the rapid detection of avalanche current. The capacitance induction quenching circuit uses SPAD parasitic capacitance to induce avalanche current which greatly reduces the layout area and uses the inverter as the detection circuit to speed up the quenching process and reduce the power consumption of the system. Both quenching circuits are designed and verified by TSMC 0.35 渭 m CMOS process. Both simulation results meet the design requirements, and can detect avalanche currents as low as 200 渭 A, reset in 2ns, and output single photon response pulses in 5ns for post-stage readout circuit processing. The results show that the quenching circuit designed in this paper has some advantages in reset and quenching time compared with the existing research results at home and abroad. The two circuits are verified by the readout circuit system with array size of 8 脳 8 and 64 脳 64, respectively. The chip test results show that both quenched circuits can induce and quench avalanche current. However, due to the effect of parasitic effect of large array system layout, there is a certain gap between the test results and the simulation results. This paper gives a detailed analysis and improvement methods.
【學(xué)位授予單位】:東南大學(xué)
【學(xué)位級別】:碩士
【學(xué)位授予年份】:2015
【分類號】:TN402;TN312.7

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