一種Vcm-Based10位16M采樣率低功耗逐次逼近型模數(shù)轉換器
發(fā)布時間：2019-05-23 22:51
【摘要】：針對無線傳感網(wǎng)絡中低功耗無線傳感器的應用,設計了一種采樣速率為16MSPS,精度10bit的全差分超低功耗逐次逼近型模數(shù)轉換器(SAR ADC).提出一種基于Vcm-Based參考電壓的開關切換邏輯,減少DAC模塊參考電壓開關切換的功耗.同時,DAC電容陣列模塊采用分段式結構,單位電容采用優(yōu)化的MOM電容,有效提高ADC的匹配性和精度;此外采用了雙尾電流型動態(tài)鎖存比較器,實現(xiàn)功耗的最優(yōu)化.芯片采用CMOS 65nm工藝設計,后仿結果顯示在1.2V電源電壓及16MSPS采樣率下,ADC有效位數(shù)達到9.42bit,功耗為140μW,品質因數(shù)(FOM)為12.8fJ/Conversion-step.
[Abstract]:Aiming at the application of low power wireless sensor in wireless sensor network, a full differential ultra low power successive approximating analog to digital converter (SAR ADC). With sampling rate of 16MSP and precision 10bit is designed. A switching logic based on Vcm-Based reference voltage is proposed to reduce the power consumption of DAC module reference voltage switch. At the same time, the DAC capacitor array module adopts the segmented structure, the unit capacitance adopts the optimized MOM capacitance, which effectively improves the matching and accuracy of ADC, in addition, the double tail current mode dynamic latch comparator is used to optimize the power consumption. The chip is designed by CMOS 65nm process. The simulation results show that the effective number of ADC is 9.42 bit, the power consumption is 140 渭 W, and the quality factor (FOM) is 12.8fJ 鈮，
本文編號：2484307
[Abstract]:Aiming at the application of low power wireless sensor in wireless sensor network, a full differential ultra low power successive approximating analog to digital converter (SAR ADC). With sampling rate of 16MSP and precision 10bit is designed. A switching logic based on Vcm-Based reference voltage is proposed to reduce the power consumption of DAC module reference voltage switch. At the same time, the DAC capacitor array module adopts the segmented structure, the unit capacitance adopts the optimized MOM capacitance, which effectively improves the matching and accuracy of ADC, in addition, the double tail current mode dynamic latch comparator is used to optimize the power consumption. The chip is designed by CMOS 65nm process. The simulation results show that the effective number of ADC is 9.42 bit, the power consumption is 140 渭 W, and the quality factor (FOM) is 12.8fJ 鈮，
本文編號：2484307
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