發(fā)布時(shí)間：2018-06-07 17:47

  本文選題：SIMD + 浮點(diǎn)算術(shù)邏輯部件��； 參考：《國(guó)防科學(xué)技術(shù)大學(xué)》2013年碩士論文

【摘要】：為了滿足高性能計(jì)算、軍事、無(wú)線通信、視頻和圖像處理等領(lǐng)域?qū)��?shù)字信號(hào)處理日益增長(zhǎng)的需求，我們自主設(shè)計(jì)了X-DSP，其是一款支持SIMD的高性能64位多核DSP，采用超長(zhǎng)指令字結(jié)構(gòu)，設(shè)計(jì)主頻為1.5GHz。本文依托X-DSP的開發(fā)與研制，旨在研究和設(shè)計(jì)面向DSP的高性能浮點(diǎn)算術(shù)邏輯部件，以滿足數(shù)字信號(hào)處理器對(duì)浮點(diǎn)算術(shù)邏輯運(yùn)算的處理需求。本文的主要工作如下： 1．對(duì)浮點(diǎn)算術(shù)邏輯部件的進(jìn)行了深入研究。針對(duì)X-DSP的需求，將浮點(diǎn)算術(shù)邏輯部件的功能分為四類，分別是比較運(yùn)算、加減法運(yùn)算、轉(zhuǎn)換運(yùn)算和特殊運(yùn)算，設(shè)計(jì)了相應(yīng)的指令集，，在此基礎(chǔ)上規(guī)劃和設(shè)計(jì)了支持單精度SIMD操作的64位高速FALU部件的整體結(jié)構(gòu)。 2．闡述了其中各個(gè)子模塊的結(jié)構(gòu)和詳細(xì)實(shí)現(xiàn)方法，研究了設(shè)計(jì)優(yōu)化的方法，并根據(jù)部件中各個(gè)模塊的特點(diǎn)，使用了不同的優(yōu)化策略進(jìn)行結(jié)構(gòu)優(yōu)化，在此基礎(chǔ)上，對(duì)部件中使用到的加法器、移位器和前導(dǎo)1預(yù)測(cè)等關(guān)鍵部件進(jìn)行了詳細(xì)的設(shè)計(jì)。 3．對(duì)浮點(diǎn)算術(shù)邏輯部件的各子模塊和整體部件進(jìn)行了詳細(xì)的功能點(diǎn)驗(yàn)證和隨機(jī)驗(yàn)證，在驗(yàn)證過(guò)程中開發(fā)了一款可視化的模塊級(jí)指令模擬器，可以極大地減少驗(yàn)證中繁瑣而重復(fù)的工作，提高了驗(yàn)證效率和準(zhǔn)確性。根據(jù)驗(yàn)證反饋的結(jié)果對(duì)部件不斷的迭代修正后，確保了功能正確性。 4．使用Cadence公司RTL Compiler工具對(duì)浮點(diǎn)算術(shù)邏輯部件及其子模塊進(jìn)行了綜合。研究了綜合的策略，在TSMC的45nm工藝下，綜合結(jié)果表明：該部件的關(guān)鍵路徑延遲450ps，cell面積47690μm2，總面積130350μm2，總功耗4.34mW。該結(jié)果表明本設(shè)計(jì)滿足X-DSP浮點(diǎn)算術(shù)邏輯部件的性能要求。
[Abstract]:In order to meet the increasing demand for digital signal processing in the fields of high performance computing, military, wireless communication, video and image processing, we have designed X-DSPs, which is a high-performance 64-bit multi-core DSPs that support SIMD. The main frequency is 1.5 GHz. Based on the development and research of X-DSP, this paper aims to study and design a high performance floating-point arithmetic logic unit for DSP in order to meet the processing requirement of digital signal processor for floating-point arithmetic logic operation. The main work of this paper is as follows: 1. The floating-point arithmetic and logic parts are deeply studied. According to the requirements of X-DSP, the functions of floating-point arithmetic logic parts are divided into four categories: comparison operation, addition and subtraction operation, conversion operation and special operation, and the corresponding instruction set is designed. On this basis, the overall structure of 64 bit high speed FALU components supporting single precision SIMD operation is planned and designed. 2. In this paper, the structure and implementation method of each sub-module are described, and the method of design optimization is studied. According to the characteristics of each module in the component, different optimization strategies are used to optimize the structure. The key components, such as adder, shifter and predictor 1, are designed in detail. 3. The function point verification and random verification of each submodule and whole part of floating-point arithmetic logic unit are carried out in detail. A visual modular-level instruction simulator is developed in the process of verification. It can greatly reduce the tedious and repetitive work in verification, and improve the efficiency and accuracy of verification. According to the results of validation feedback, the components are iterated and modified to ensure the correctness of the function. 4. 4. The floating-point arithmetic logic unit and its sub-modules are synthesized by Cadence RTL Compiler tool. The synthesis strategy is studied. The synthesis results show that the critical path delay of the component is 47690 渭 m ~ (2), the total area is 130350 渭 m ~ (2), and the total power consumption is 4.34 MW. The results show that the design meets the performance requirements of X-DSP floating-point arithmetic logic unit.
【學(xué)位授予單位】：國(guó)防科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類號(hào)】：TP332.2

【參考文獻(xiàn)】

相關(guān)博士學(xué)位論文 前1條

1 李振濤;高性能DSP關(guān)鍵電路及EDA技術(shù)研究[D];國(guó)防科學(xué)技術(shù)大學(xué);2007年

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