發(fā)布時間：2018-06-07 17:47

  本文選題：SIMD + 浮點算術邏輯部件�。� 參考：《國防科學技術大學》2013年碩士論文

【摘要】：為了滿足高性能計算、軍事、無線通信、視頻和圖像處理等領域對數字信號處理日益增長的需求，我們自主設計了X-DSP，其是一款支持SIMD的高性能64位多核DSP，采用超長指令字結構，設計主頻為1.5GHz。本文依托X-DSP的開發(fā)與研制，旨在研究和設計面向DSP的高性能浮點算術邏輯部件，以滿足數字信號處理器對浮點算術邏輯運算的處理需求。本文的主要工作如下： 1．對浮點算術邏輯部件的進行了深入研究。針對X-DSP的需求，將浮點算術邏輯部件的功能分為四類，分別是比較運算、加減法運算、轉換運算和特殊運算，設計了相應的指令集，，在此基礎上規(guī)劃和設計了支持單精度SIMD操作的64位高速FALU部件的整體結構。 2．闡述了其中各個子模塊的結構和詳細實現(xiàn)方法，研究了設計優(yōu)化的方法，并根據部件中各個模塊的特點，使用了不同的優(yōu)化策略進行結構優(yōu)化，在此基礎上，對部件中使用到的加法器、移位器和前導1預測等關鍵部件進行了詳細的設計。 3．對浮點算術邏輯部件的各子模塊和整體部件進行了詳細的功能點驗證和隨機驗證，在驗證過程中開發(fā)了一款可視化的模塊級指令模擬器，可以極大地減少驗證中繁瑣而重復的工作，提高了驗證效率和準確性。根據驗證反饋的結果對部件不斷的迭代修正后，確保了功能正確性。 4．使用Cadence公司RTL Compiler工具對浮點算術邏輯部件及其子模塊進行了綜合。研究了綜合的策略，在TSMC的45nm工藝下，綜合結果表明：該部件的關鍵路徑延遲450ps，cell面積47690μm2，總面積130350μm2，總功耗4.34mW。該結果表明本設計滿足X-DSP浮點算術邏輯部件的性能要求。
[Abstract]:In order to meet the increasing demand for digital signal processing in the fields of high performance computing, military, wireless communication, video and image processing, we have designed X-DSPs, which is a high-performance 64-bit multi-core DSPs that support SIMD. The main frequency is 1.5 GHz. Based on the development and research of X-DSP, this paper aims to study and design a high performance floating-point arithmetic logic unit for DSP in order to meet the processing requirement of digital signal processor for floating-point arithmetic logic operation. The main work of this paper is as follows: 1. The floating-point arithmetic and logic parts are deeply studied. According to the requirements of X-DSP, the functions of floating-point arithmetic logic parts are divided into four categories: comparison operation, addition and subtraction operation, conversion operation and special operation, and the corresponding instruction set is designed. On this basis, the overall structure of 64 bit high speed FALU components supporting single precision SIMD operation is planned and designed. 2. In this paper, the structure and implementation method of each sub-module are described, and the method of design optimization is studied. According to the characteristics of each module in the component, different optimization strategies are used to optimize the structure. The key components, such as adder, shifter and predictor 1, are designed in detail. 3. The function point verification and random verification of each submodule and whole part of floating-point arithmetic logic unit are carried out in detail. A visual modular-level instruction simulator is developed in the process of verification. It can greatly reduce the tedious and repetitive work in verification, and improve the efficiency and accuracy of verification. According to the results of validation feedback, the components are iterated and modified to ensure the correctness of the function. 4. 4. The floating-point arithmetic logic unit and its sub-modules are synthesized by Cadence RTL Compiler tool. The synthesis strategy is studied. The synthesis results show that the critical path delay of the component is 47690 渭 m ~ (2), the total area is 130350 渭 m ~ (2), and the total power consumption is 4.34 MW. The results show that the design meets the performance requirements of X-DSP floating-point arithmetic logic unit.
【學位授予單位】：國防科學技術大學
【學位級別】：碩士
【學位授予年份】：2013
【分類號】：TP332.2

【參考文獻】

相關博士學位論文 前1條

1 李振濤;高性能DSP關鍵電路及EDA技術研究[D];國防科學技術大學;2007年

本文編號：1992145