光接收芯片內時鐘數據恢復電路的設計
發(fā)布時間：2018-09-12 18:40
【摘要】：光纖通訊具有容量大、抗干擾能力強、傳輸距離遠、節(jié)能等優(yōu)點,成為目前研究的熱門課題。在光纖通訊的過程中,需要時鐘數據恢復電路提取時鐘,并對數據進行重定時以抑制抖動。目前我國的主流光纖傳輸速率是2.5Gbps,隨著光纖傳輸的速度和要求逐步提升,10Gbps的光纖傳輸速率必將成為未來的主流。因此本論文的主要目標是設計一款中心頻率為10Gbps的時鐘數據恢復(CDR)電路芯片。論文采用鎖相環(huán)為基礎的時鐘數據恢復電路結構,電路包括鑒頻器(FD)、鑒相器(PD)、低通濾波器(LPF)、電荷泵(CP)、壓控振蕩器(VCO)以及重定時模塊。為減少抖動積累并產生高頻振蕩,采用低噪聲結構的LC壓控振蕩器產生高頻時鐘信號。在電荷泵模塊設立參考電平,保證控制電壓的變化幅度限制在壓控振蕩器的線性區(qū)以內。鑒頻器采用下降選頻的新型結構以達到1.35GHz的超大范圍頻率捕捉,鑒相器采用前置D觸發(fā)器優(yōu)化過零點,并使時鐘信號保持在數據位中間點采樣,為抖動和不確定因素提供最大的裕度。鑒頻器和鑒相器可在頻率逼近后完成工作切換,縮短捕捉時間,提升了工作效率。通過調節(jié)環(huán)路參數使系統(tǒng)達到鎖定。輸入數據經過提取后的時鐘重定時,輸出抖動大大降低。在Cadence下對時鐘數據恢復電路各個模塊及整體進行了仿真分析,并給出了基于TSMC 0.18μm工藝的版圖繪制和后仿真。前仿真結果表明,本文所設計的時鐘數據恢復電路在3.3V的電源電壓下整體功耗為90mW,恢復出的10GHz時鐘相位噪聲為-87.5dBc/Hz,壓控振蕩器壓控增益為1.08GHz/V。在系統(tǒng)鎖定后,輸出時鐘的峰峰值抖動為3ps,重定時后的數據輸出抖動峰峰值為4.5ps。芯片版圖面積為300μm×500μm,后仿真結果表明,系統(tǒng)鎖定后輸出時鐘峰峰值抖動為6ps,重定時后的數據輸出峰峰值抖動為10ps,對比輸入數據15ps抖動,起到了很好的抖動抑制效果。
[Abstract]:Optical fiber communication has many advantages, such as large capacity, strong anti-interference ability, long transmission distance, energy saving and so on. In the process of optical fiber communication, the clock data recovery circuit is needed to extract the clock and retiming the data to suppress the jitter. At present, the main fiber transmission rate in China is 2.5Gbps.With the speed and requirement of fiber transmission, the fiber transmission rate of 10Gbps will become the mainstream in the future. Therefore, the main goal of this thesis is to design a clock data recovery (CDR) chip with center frequency of 10Gbps. In this paper, a clock data recovery circuit based on PLL is used. The circuit includes a frequency discriminator, a (FD), phase discriminator, a (PD), low-pass filter, a (LPF), charge pump (CP), voltage-controlled oscillator (VCO) and a retiming module. In order to reduce jitter accumulation and generate high frequency oscillation, a low noise LC voltage-controlled oscillator is used to generate high frequency clock signal. The reference level is set up in the charge pump module to ensure that the range of the control voltage is limited to the linear range of the VCO. The frequency discriminator adopts a new structure of descending frequency selection to achieve the 1.35GHz super wide frequency capture. The phase detector uses a preposition D flip-flop to optimize the zero crossing point and to keep the clock signal sampling at the middle of the data bit. Provides maximum margin for jitter and uncertainty. Frequency discriminator and phase discriminator can complete the switching after frequency approaching, shorten the capture time and improve the working efficiency. The system is locked by adjusting the loop parameters. After the input data is extracted, the output jitter is greatly reduced when the clock is retimed. Each module and whole of clock data recovery circuit are simulated and analyzed in Cadence, and the layout drawing and post simulation based on TSMC 0.18 渭 m technology are given. The pre-simulation results show that the overall power consumption of the designed clock data recovery circuit is 90 MW at 3.3 V supply voltage, the recovered 10GHz clock phase noise is -87.5 dBc / Hz, and the voltage control gain of the VCO is 1.08 GHz / V. After the system is locked, the peak jitter of the output clock is 3 pss, and the peak value of the data output jitter after retiming is 4.5 ps. The chip layout area is 300 渭 m 脳 500 渭 m. The post-simulation results show that the peak jitter of the output clock peak is 6 pss after locking and the peak jitter of the data output peak after retiming is 10 ps.Compared with the 15ps jitter of input data, the jitter suppression effect is very good.
【學位授予單位】：哈爾濱工業(yè)大學
【學位級別】：碩士
【學位授予年份】：2017
【分類號】：TN929.11;TN402
本文編號：2239899
[Abstract]:Optical fiber communication has many advantages, such as large capacity, strong anti-interference ability, long transmission distance, energy saving and so on. In the process of optical fiber communication, the clock data recovery circuit is needed to extract the clock and retiming the data to suppress the jitter. At present, the main fiber transmission rate in China is 2.5Gbps.With the speed and requirement of fiber transmission, the fiber transmission rate of 10Gbps will become the mainstream in the future. Therefore, the main goal of this thesis is to design a clock data recovery (CDR) chip with center frequency of 10Gbps. In this paper, a clock data recovery circuit based on PLL is used. The circuit includes a frequency discriminator, a (FD), phase discriminator, a (PD), low-pass filter, a (LPF), charge pump (CP), voltage-controlled oscillator (VCO) and a retiming module. In order to reduce jitter accumulation and generate high frequency oscillation, a low noise LC voltage-controlled oscillator is used to generate high frequency clock signal. The reference level is set up in the charge pump module to ensure that the range of the control voltage is limited to the linear range of the VCO. The frequency discriminator adopts a new structure of descending frequency selection to achieve the 1.35GHz super wide frequency capture. The phase detector uses a preposition D flip-flop to optimize the zero crossing point and to keep the clock signal sampling at the middle of the data bit. Provides maximum margin for jitter and uncertainty. Frequency discriminator and phase discriminator can complete the switching after frequency approaching, shorten the capture time and improve the working efficiency. The system is locked by adjusting the loop parameters. After the input data is extracted, the output jitter is greatly reduced when the clock is retimed. Each module and whole of clock data recovery circuit are simulated and analyzed in Cadence, and the layout drawing and post simulation based on TSMC 0.18 渭 m technology are given. The pre-simulation results show that the overall power consumption of the designed clock data recovery circuit is 90 MW at 3.3 V supply voltage, the recovered 10GHz clock phase noise is -87.5 dBc / Hz, and the voltage control gain of the VCO is 1.08 GHz / V. After the system is locked, the peak jitter of the output clock is 3 pss, and the peak value of the data output jitter after retiming is 4.5 ps. The chip layout area is 300 渭 m 脳 500 渭 m. The post-simulation results show that the peak jitter of the output clock peak is 6 pss after locking and the peak jitter of the data output peak after retiming is 10 ps.Compared with the 15ps jitter of input data, the jitter suppression effect is very good.
【學位授予單位】：哈爾濱工業(yè)大學
【學位級別】：碩士
【學位授予年份】：2017
【分類號】：TN929.11;TN402
【參考文獻】
相關期刊論文 前6條
1 羅林;孟煦;劉認;林福江;;一種低抖動低雜散的亞采樣鎖相環(huán)[J];微電子學;2017年01期
2 LI Xuan;WU Xiulong;CHEN Junning;;New Design Method of LC VCO Improving PVT Tolerance of Phase Noise[J];Chinese Journal of Electronics;2015年03期
3 羅將;何進;吳歡成;王豪;常勝;黃啟俊;熊永忠;;43GHz低功耗和低相噪VCO設計[J];微電子學與計算機;2015年07期
4 王旭;朱紅衛(wèi);;一種用于時鐘數據恢復的寬帶鎖相環(huán)設計[J];電子器件;2013年06期
5 劉永旺;王志功;李偉;;2.5Gbps/ch兩通道并行時鐘數據恢復電路[J];半導體學報;2007年03期
6 陳瑩梅;王志功;趙海兵;章麗;熊明珍;;10Gb/sCMOS時鐘和數據恢復電路的設計[J];固體電子學研究與進展;2005年04期
相關博士學位論文 前2條
1 梁亮;低電壓CMOS分數分頻鎖相環(huán)頻率綜合器關鍵技術研究[D];西安電子科技大學;2016年
2 唐長文;電感電容壓控振蕩器[D];復旦大學;2004年
相關碩士學位論文 前2條
1 杜云飛;用于時鐘信號發(fā)生的鎖相環(huán)電路的設計[D];哈爾濱工業(yè)大學;2015年
2 劉期若;基于PLL的時鐘數據恢復電路設計[D];哈爾濱工業(yè)大學;2010年
，本文編號：2239899
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