基于可重構(gòu)的密碼算法的設(shè)計(jì)與實(shí)現(xiàn)
發(fā)布時(shí)間：2019-03-11 10:17
【摘要】：隨著信息科技的快速發(fā)展,信息安全越來越受到人們的關(guān)注,密碼技術(shù)是保障信息安全的核心技術(shù)。可重構(gòu)計(jì)算技術(shù)應(yīng)用于密碼處理系統(tǒng),使同一硬件實(shí)現(xiàn)多種密碼算法,既滿足了密碼算法處理對(duì)性能的要求,同時(shí)又具有較高的靈活性,提高了密碼系統(tǒng)的安全性,在商業(yè)以及軍事等領(lǐng)域具有廣闊的應(yīng)用空間。本文深入分析了分組密碼算法AES、 DES和哈希算法SHA-3的處理結(jié)構(gòu)特點(diǎn)及基本操作特征,結(jié)合可重構(gòu)計(jì)算結(jié)構(gòu)的設(shè)計(jì)特點(diǎn)與方法,設(shè)計(jì)了一種實(shí)現(xiàn)AES、 DES和SHA-3算法的可重構(gòu)密碼處理結(jié)構(gòu)RCPA.該結(jié)構(gòu)主要包括可重構(gòu)處理單元PE、控制配置單元CCU、存儲(chǔ)單元MU、輸入輸出緩沖單元IOBU以及互聯(lián)單元ICU。本文研究了三種密碼算法的基本運(yùn)算單元,對(duì)具有相似的運(yùn)算單元進(jìn)行了研究分析,設(shè)計(jì)了可重構(gòu)基本處理單元�？芍貥�(gòu)基本處理單元根據(jù)控制配置信息進(jìn)行重構(gòu),靈活完成不同密碼算法所需的運(yùn)算功能。論文基于Verilog HDL硬件描述語言對(duì)該可重構(gòu)密碼處理結(jié)構(gòu)進(jìn)行了原型設(shè)計(jì),詳述了AES、 DES和SHA-3密碼算法在可重構(gòu)密碼處理結(jié)構(gòu)上的優(yōu)化與映射過程。該設(shè)計(jì)原型在Cyclone IV系列FPGA器件上進(jìn)行了板級(jí)驗(yàn)證,并在65nm CMOS工藝標(biāo)準(zhǔn)單元庫下進(jìn)行了邏輯綜合。根據(jù)ASIC綜合性能和在RCPA上的映射結(jié)果,給出了500MHz時(shí)鐘頻率下三種密碼算法的執(zhí)行性能。實(shí)驗(yàn)結(jié)果表明,本文設(shè)計(jì)的針對(duì)AES、 DES和SHA-3密碼算法的可重構(gòu)密碼處理結(jié)構(gòu)具有較高的處理性能。其密碼處理速度與一些專用可重構(gòu)密碼結(jié)構(gòu)相比性能提高了3.7～4.4倍：與其它一些ASIC實(shí)現(xiàn)的密碼處理芯片相比,接近其80%的處理性能。結(jié)果說明本文研究的RCPA既能保證密碼算法應(yīng)用的靈活性,又能達(dá)到較高的處理性能。
[Abstract]:With the rapid development of information technology, people pay more and more attention to information security. Cryptography is the core technology to guarantee information security. The reconfigurable computing technology is applied to the cryptographic processing system, which enables the same hardware to implement a variety of cryptographic algorithms, not only satisfies the performance requirements of cryptographic algorithm processing, but also has high flexibility, and improves the security of the cryptosystem. It has a wide range of applications in commercial and military fields. In this paper, the processing structure and basic operation characteristics of block cipher algorithm AES, DES and hash algorithm SHA-3 are analyzed in depth. Combined with the design characteristics and methods of reconfigurable computing structure, a realization of AES, is designed. The Reconfigurable Cipher processing Architecture of DES and SHA-3 algorithms RCPA. The structure mainly includes reconfigurable processing unit PE, control configuration unit CCU, storage unit MU, input and output buffer unit IOBU and interconnection unit ICU. In this paper, the basic operation units of three cryptographic algorithms are studied, the similar operation units are studied and analyzed, and the reconfigurable basic processing units are designed. The reconfigurable basic processing unit reconstructs according to the control configuration information and flexibly accomplishes the operation functions required by different cryptographic algorithms. In this paper, the prototype of the reconfigurable cryptosystem is designed based on Verilog HDL hardware description language, and the optimization and mapping process of AES, DES and SHA-3 cryptographic algorithms in reconfigurable cryptosystem are described in detail. The prototype is verified at the board level on Cyclone IV series FPGA devices, and the logic synthesis is carried out under the 65nm CMOS process standard cell library. According to the comprehensive performance of ASIC and the mapping results on RCPA, the performance of three cryptographic algorithms at 500MHz clock frequency is given. The experimental results show that the reconfigurable cryptographic structure designed in this paper for AES, DES and SHA-3 cryptographic algorithms has high processing performance. Compared with some special reconfigurable cryptosystems, the performance of cryptographic processing is 3. 7-4. 4 times higher than that of some other ASIC-implemented cryptographic chips, which is close to 80% of its processing performance. The results show that the RCPA can not only guarantee the flexibility of cryptographic algorithm application, but also achieve high processing performance.
【學(xué)位授予單位】：東南大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2016
【分類號(hào)】：TN918.1
本文編號(hào)：2438203
[Abstract]:With the rapid development of information technology, people pay more and more attention to information security. Cryptography is the core technology to guarantee information security. The reconfigurable computing technology is applied to the cryptographic processing system, which enables the same hardware to implement a variety of cryptographic algorithms, not only satisfies the performance requirements of cryptographic algorithm processing, but also has high flexibility, and improves the security of the cryptosystem. It has a wide range of applications in commercial and military fields. In this paper, the processing structure and basic operation characteristics of block cipher algorithm AES, DES and hash algorithm SHA-3 are analyzed in depth. Combined with the design characteristics and methods of reconfigurable computing structure, a realization of AES, is designed. The Reconfigurable Cipher processing Architecture of DES and SHA-3 algorithms RCPA. The structure mainly includes reconfigurable processing unit PE, control configuration unit CCU, storage unit MU, input and output buffer unit IOBU and interconnection unit ICU. In this paper, the basic operation units of three cryptographic algorithms are studied, the similar operation units are studied and analyzed, and the reconfigurable basic processing units are designed. The reconfigurable basic processing unit reconstructs according to the control configuration information and flexibly accomplishes the operation functions required by different cryptographic algorithms. In this paper, the prototype of the reconfigurable cryptosystem is designed based on Verilog HDL hardware description language, and the optimization and mapping process of AES, DES and SHA-3 cryptographic algorithms in reconfigurable cryptosystem are described in detail. The prototype is verified at the board level on Cyclone IV series FPGA devices, and the logic synthesis is carried out under the 65nm CMOS process standard cell library. According to the comprehensive performance of ASIC and the mapping results on RCPA, the performance of three cryptographic algorithms at 500MHz clock frequency is given. The experimental results show that the reconfigurable cryptographic structure designed in this paper for AES, DES and SHA-3 cryptographic algorithms has high processing performance. Compared with some special reconfigurable cryptosystems, the performance of cryptographic processing is 3. 7-4. 4 times higher than that of some other ASIC-implemented cryptographic chips, which is close to 80% of its processing performance. The results show that the RCPA can not only guarantee the flexibility of cryptographic algorithm application, but also achieve high processing performance.
【學(xué)位授予單位】：東南大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2016
【分類號(hào)】：TN918.1
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